Certain types of memory devices require a clock strobe signal having edges that are aligned with the center of changes in the write data. A double data rate (DDR) dynamic random access memory (DRAM) registers data on each rising and falling edge of the clock strobe signal. A DDR DRAM therefore accepts or registers two data words per clock cycle.
A memory controller is often used to coordinate the transfer of data to and from a memory device, such as a DDR DRAM. The memory controller provides a clock strobe signal to the memory device for synchronizing write operations. The memory device uses the clock strobe signal for determining when the write data is valid and can therefore be latched. As mentioned, data to a DDR DRAM transitions twice per clock period. Ideally, data to a DDR DRAM transitions with a ¼ clock phase shift from the data clock strobe as measured at the memory device. The memory controller is responsible for creating this phase shift with appropriate timing to insure correct operation of the memory device. In previous controllers, the controller has used a clock signal having two times (2×) the frequency of a system clock signal. A current approach to creating the desired phase shift is to invert the 2× clock signal, and to use the falling edge of the inverted 2× clock as the event that transitions write data to the memory device. This approach can have certain limitations and/or can necessitate added circuit complexity.
Clock generation circuits, such as oscillators or phase locked loops (PLLs), coupled with asymmetries introduced by clock tree routing, do not provide a uniform duty cycle (i.e., the time that the clock signal is observed as being high is different than the time the clock signal is observed as being low). When a uniform duty cycle is important, a clock of twice the desired frequency (i.e., the 2× clock) may be used and divided by two to create a symmetrical clock. In the case of DDR DRAM, this would require the generation and distribution of a 4× clock, which is not desirable due to the high frequencies involved. If an asymmetrical duty cycle 2× clock is used to align the write data, the operational frequency of the memory can be limited and the resulting system will have less margin surrounding timing of write data with respect to the data clock strobes. Improved memory controller circuits are therefore desired that are capable of aligning write data provided to a memory device, with respect to a data clock strobe signal that is generated from the memory controller, without one or more of the aforementioned limitations or requirements.